What does claim 1 of US 2008/0255822 A1 cover?

Question

In reference to the patent: US 2008/0255822 A1

Does this patent mean that no-one can do another architecture coverage driven test generator for ARM cores?

This patent is quite generic and I believe that it covers all possible test generators based on architecture features.

If I want to make a automatic architecture Coverage driven random test generator for ARM architecture do I have conflict with that patent?

Google Patents lists the first claim as,

A method for automatically creating compliance test suites for a processor, comprising the steps of:

constructing a generic model set for a plurality of implementations of a processor architecture, said generic model set comprising one or more parametric models being adapted to a model-based test generator, wherein said processor architecture permits selection among multiple options for said implementations, and said implementations each exhibit a respective alternative behavior corresponding to selected ones of said options;

based on said generic model set, establishing specific model sets to correspond to said respective alternative behavior of said implementations by setting respective values of parameters for said parametric models;

producing test specifications using said parametric models and said values;

submitting said test specifications to said test generator; and

generating respective architectural compliance test suites for said implementations with said test generator using said test specifications, wherein said test generator is cooperative with said parametric models using said values to predict expected outcomes in an execution of said respective architectural compliance test suites by said implementations.

Answer 1

The document that you are referencing is just the patent application publication from the pending application. This application issued as US Pat. US8280713B2 The claims from the issued patent are the ones that are enforceable and are much more narrow than the claims in the publication.

To determine whether possible infringement is present. See if your proposed product has all elements of the claims. For example, claim 1 is below. Claims 10 and 17 are the other independent claims, but also consider the dependent claims. Talk with an attorney to get a proper analysis if necessary.

1. A method for automatically creating compliance test suites for a processor, comprising the steps of:

   constructing a generic model set for a plurality of implementations of a processor architecture, said generic model set comprising one or more parametric models and being adapted to a model-based test generator, wherein said processor architecture specifies selectable options which, when selected, produce respective alternative behaviors of said implementations;

   establishing a deviation model that indicates a selection of at least one of the options, wherein said deviation model comprises a set of deviation parameters that are reflective of said one option, and wherein said parametric models are responsive to said deviation parameters of said deviation model so as to enable respective alternative behaviors of the implementations that embody the one option;

   based on said generic model set, establishing specific coverage model sets to correspond to said respective alternative behaviors of said implementations; responsively to said deviation model, modifying said generic model set and said coverage model sets by setting respective values of parameters for said parametric models and said coverage model sets;

   producing test specifications using said parametric models and said coverage model sets;

   submitting said test specifications to said test generator; and generating respective architectural compliance test suites for said implementations with said test generator using said test specifications, wherein said test generator is cooperative with said parametric models using said values to predict expected outcomes in an execution of said respective architectural compliance test suites by a simulator of said implementations.